Backside mold process for ultra thin substrate and package on package assembly

ABSTRACT

In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, forming a stiffening mold on a backside of the coreless substrate strip adjacent to sites where solder balls are to be attached, and attaching solder balls to the backside of the coreless substrate strip amongst the stiffening mold. Other embodiments are also disclosed and claimed.

PRIORITY APPLICATION

This application is a continuation of U.S. application Ser. No.13/776,189, filed Feb. 25, 2013, which is a divisional of U.S.application Ser. No. 12/164,390, filed Jun. 30, 2008, now issued as U.S.Pat. No. 8,384,223, all of which are incorporated herein by reference intheir entirety.

FIELD OF THE INVENTION

Embodiments of the present invention generally relate to the field ofintegrated circuit packages, and, more particularly to backside moldprocess for ultra thin substrate and package on package assembly.

BACKGROUND OF THE INVENTION

As microelectronic components shrink in size, a trend has emerged toprovide package substrates that may be characterized as thin coresubstrates (that is, substrates having a core with a thickness less thanor equal to 400 microns and larger than zero), or no-core substrates(that is, substrates without cores).

Disadvantageously, with a thin or no-core substrate, however, decreasein yield at first level chip attach due to warpage causing nonwets mayoccur during the package manufacturing process, such as, for example,during flip chip bonding where substrate flatness and rigidity arerequired. To address the above issue, the prior art sometimes providessubstrates that may have a thickness of at least several tens of micronsor more. However, the above measure disadvantageously detracts fromfurther package size minimization.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and notlimitation in the figures of the accompanying drawings in which likereferences indicate similar elements, and in which:

FIG. 1 is a graphical illustration of a cross-sectional view of apartially formed IC package, in accordance with one example embodimentof the invention;

FIG. 2 is a graphical illustration of a cross-sectional view of apartially formed IC package, in accordance with one example embodimentof the invention;

FIG. 3 is a graphical illustration of a cross-sectional view of apartially formed IC package, in accordance with one example embodimentof the invention;

FIG. 4 is a graphical illustration of a cross-sectional view of apartially formed IC package, in accordance with one example embodimentof the invention;

FIG. 5 is a graphical illustration of a cross-sectional view of apartially formed IC package, in accordance with one example embodimentof the invention;

FIG. 6 is a graphical illustration of a cross-sectional view of apartially formed IC package, in accordance with one example embodimentof the invention;

FIG. 7 is a graphical illustration of a cross-sectional view of apartially formed IC package, in accordance with one example embodimentof the invention; and

FIG. 8 is a graphical illustration of a cross-sectional view of apartially formed IC package, in accordance with one example embodimentof the invention.

DETAILED DESCRIPTION

In the following description, for purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of the invention. It will be apparent, however, to oneskilled in the art that embodiments of the invention can be practicedwithout these specific details. In other instances, structures anddevices are shown in block diagram form in order to avoid obscuring theinvention.

Reference throughout this specification to “one embodiment” or “anembodiment” means that a particular feature, structure or characteristicdescribed in connection with the embodiment is included in at least oneembodiment of the present invention. Thus, appearances of the phrases“in one embodiment” or “in an embodiment” in various places throughoutthis specification are not necessarily all referring to the sameembodiment. Furthermore, the particular features, structures orcharacteristics may be combined in any suitable manner in one or moreembodiments.

FIG. 1 is a graphical illustration of a cross-sectional view of apartially formed IC package, in accordance with one example embodimentof the invention. In accordance with the illustrated example embodiment,package 100 includes one or more of coreless substrate strip 102,backside contacts 104, topside contacts 106 and substrate thickness 108.

Coreless substrate strip 102 represents a thin substrate that may berolled out and processed before being singulated. In one embodiment,coreless substrate strip 102 is a direct laser lamination generation 3(DLL3) strip. In one embodiment, substrate thickness 108 is about 200micrometers.

FIG. 2 is a graphical illustration of a cross-sectional view of apartially formed IC package, in accordance with one example embodimentof the invention. As shown in package 200, mold compound 202 isdispensed as a liquid on backside 206 and compressed by mold form 204.In one embodiment, mold form 204 is a jig designed to compress moldcompound 202 adjacent to sites where solder balls are to be attached.Mold form 204 may be held in place for some time and may be heated toallow mold compound 202 to cure.

FIG. 3 is a graphical illustration of a cross-sectional view of apartially formed IC package, in accordance with one example embodimentof the invention. As shown in package 300, stiffening mold 302 is curedand provides added stiffness to package 300. In one embodiment,stiffening mold 302 has a mold thickness 304 of about 100 micrometers.

FIG. 4 is a graphical illustration of a cross-sectional view of apartially formed IC package, in accordance with one example embodimentof the invention. As shown in package 400, solder balls 402 have beenattached amongst stiffening mold 302. In one embodiment, solder balldiameter 404 is about 10 mils. In one embodiment, solder balls 402 aremade from a high melting point solder (higher than about 220 degreesCelsius) so as to maintain their integrity through subsequent reflows,for example, a reflow for attaching a topside integrated circuit device.In another embodiment, solder balls 402 are not attached until later inthe process after an integrated circuit device has been attached.

FIG. 5 is a graphical illustration of a cross-sectional view of apartially formed IC package, in accordance with one example embodimentof the invention. As shown in package 500, the package has been flippedover for topside processing.

FIG. 6 is a graphical illustration of a cross-sectional view of apartially formed IC package, in accordance with one example embodimentof the invention. As shown in package 600, integrated circuit device 602has been attached to topside 604 of coreless substrate strip 102.Integrated circuit device 602 may represent any type of siliconprocessor or controller or logic.

FIG. 7 is a graphical illustration of a cross-sectional view of apartially formed IC package, in accordance with one example embodimentof the invention. As shown in package 700, underfill material 702 hasbeen dispensed under integrated circuit device 602.

FIG. 8 is a graphical illustration of a cross-sectional view of apartially formed IC package, in accordance with one example embodimentof the invention. As shown in package 800, second integrated circuitdevice package 802 has been attached to topside 604 through solder balls804. Second integrated circuit device package 802 may be any type ofpackage and need not be a flip chip package.

In one embodiment, package 800 is processed further and singulated fromother packages.

In the description above, for the purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of the present invention. It will be apparent, however, toone skilled in the art that the present invention may be practicedwithout some of these specific details. In other instances, well-knownstructures and devices are shown in block diagram form.

Many of the methods are described in their most basic form butoperations can be added to or deleted from any of the methods andinformation can be added or subtracted from any of the describedmessages without departing from the basic scope of the presentinvention. Any number of variations of the inventive concept isanticipated within the scope and spirit of the present invention. Inthis regard, the particular illustrated example embodiments are notprovided to limit the invention but merely to illustrate it. Thus, thescope of the present invention is not to be determined by the specificexamples provided above but only by the plain language of the followingclaims.

What is claimed is:
 1. A method comprising: receiving a corelesssubstrate strip; and forming a stiffening mold on a backside of thecoreless substrate strip adjacent to sites where solder balls are to beattached; and attaching solder balls to the backside of the corelesssubstrate strip amongst the stiffening mold.
 2. The method of claim 1,wherein forming a stiffening mold on a backside of the corelesssubstrate strip adjacent to sites where solder balls are to be attachedcomprises: dispensing a liquid mold compound; and compressing the liquidmold compound with a jig.
 3. The method of claim 1, wherein the corelesssubstrate strip comprises a direct laser lamination generation 3 (DLL3)strip.
 4. The method of claim 1, further comprising attaching anintegrated circuit device to a topside of the coreless substrate strip.5. The method of claim 4, further comprising attaching a secondintegrated circuit device package to the topside of the corelesssubstrate strip.
 6. A method comprising: receiving a direct laserlamination generation 3 (DLL3) substrate strip; and forming a stiffeningmold on a backside of the DLL3 substrate strip adjacent to sites wheresolder balls are to be attached; and attaching solder balls to thebackside of the coreless substrate strip amongst the stiffening mold. 7.The method of claim 6, wherein the DLL3 substrate strip comprises athickness of about 200 micrometers.
 8. The method of claim 6 wherein thebackside stiffening mold comprises a thickness of about 100 micrometers.9. The method of claim 6, wherein forming a stiffening mold on abackside of the DLL3 substrate strip adjacent to sites where solderballs are to be attached comprises: dispensing a liquid mold compound;and compressing the liquid mold compound with a jig.
 10. The method ofclaim 6, further comprising attaching an integrated circuit device to atopside of the coreless substrate strip.
 11. The method of claim 10,further comprising attaching a second integrated circuit device packageto the topside of the coreless substrate strip.
 12. A method comprising:dispensing a liquid mold compound adjacent to contact sites for solderballs on a coreless substrate strip; curing the liquid mold compound toform a stiffening mold; and attaching solder balls to the backside ofthe coreless substrate strip amongst the stiffening mold.
 13. The methodof claim 12, wherein dispensing a liquid mold compound adjacent tocontact sites for solder balls on a coreless substrate strip includesdispensing a liquid mold compound on a direct laser laminationgeneration 3 (DLL3) strip.
 14. The method of claim 12, further includingcompressing the liquid mold compound with a jig to form the stiffeningmold.